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? semiconductor components industries, llc, 2003 april, 2003 - rev. 2 1 publication order number: and8076/d and8076/d a 70 w low standby power supply with the ncp120x series prepared by: christophe basso on semiconductor introduction the ncp1200 represents one of the cheapest solutions to build efficient and cost-effective switch-mode power supplies (smps). as this design example will show, the part definition does not confine the component in low-power applications only, but it can actually be used in flyback and forward supplies for virtually any output power. the below example depicts a universal mains 90-260 vac power supply delivering 16.5 v @ 4.5 a. beside its ease of implementation, the ncp1200 excels in true low standby power designs. this application note details how an amazing standby power of less than 100 mw can be reached at high line with a nominal 70 w board. dss or not dss? the dynamic self supply (dss) lets you directly drive mosfets from the high-voltage rail. this option brings you several advantages, as stated below: ? true overload detection : with uc384x-based systems, the switching oscillations are stopped in case the vcc line drops below a given undervoltage lockout level (uvlo). this principle considers a good coupling between the primary auxiliary winding and the power secondary winding. unfortunately, leakage elements often degrade this coupling and you only can detect true short-circuit (when vout is close to zero) and not overload conditions. thanks to the dss, the ncp1200 does not need an auxiliary information to sense an overload condition. by detecting a current setpoint pushed to the maximum, the internal logic takes the decision to enter into a safe burst operation, auto-recovering when the default leaves. precise overload levels can thus be implemented. ? guaranteed operation at low output levels : the vcc delivered by an auxiliary winding moves with the power output level because a coupling exists between both windings. when the supply is used in battery charging applications, vout can move depending on the charging state. that is to say, when the battery is nearly empty, its voltage can be close to zero, forcing vout at this level. thanks to the natural secondary / auxiliary reflection, the primary auxiliary winding cannot maintain a sufficient voltage on the control ic: vcc collapses and puts the controller in trouble, probably entering an hiccup mode, similar to that of a startup sequence. dss being decoupled from vout, you never see that phenomenon. as you can see, the dss offers interesting features but, on the other hand, it can sometimes compromise key design parameters. standby power and power dissipation are one of these: ? standby power : the dss standby power contribution can easily be evaluated: v hv i avg with i avg , the current consumption taken by the controller and v hv , the high-voltage supply rail. if i avg equals 1 ma, then we have a standby power of 350 mw at a 350 vdc voltage rail. tricks exist to slightly reduce it, like the half-wave diode, but you will only gain between 2030%. ? power dissipation : as stated above, all the current consumed by the ic is seen through pin8. this is due to the self-adaptive feature of the dss. should the ic current move up or down, the dss duty-cycle will automatically adjust to deliver it. the controller current depends on the internal ic consumption, but also on the type of mosfet connected to the output. it therefore important to assess the total current drawn from the hv rail and checks the right compatibility with the package type. all details are given in the ncp1200 dedicated data sheet and the application note and8023/d. as a result, the answer lies behind your design constraints. if you would like to have a precise over current protection (ocp) trip point while driving a moderate size mosfet, dss can be a good choice, provided low standby power is not an absolute necessity. in our case, we want to drive a large mosfet for a better efficiency but we need to reach the lowest possible standby power. we will thus adopt an auxiliary winding configuration to permanently disable the dss. solutions to various combinations of these constraints are described in the application note tips and tricks for the ncp1200,o document number and8069/d. application note http://onsemi.com
and8076/d http://onsemi.com 2 self-powering the controller in standby an auxiliary winding does not usually cause any self-supply problem with a continuous pulses flow. in standby, whatever implemented frequency reduction techniques (e.g. skip or frequency foldback), the recurrence between pulses can become very low. by definition, the feedback loop manages to keep the energy content in each burst high enough to maintain the nominal output voltage. however, on the auxiliary side, it can be difficult to keep the vcc above the controller's uvlo. remember, to permanently disable the dss, you need to guarantee a level above vccon max. which is 11 v for the ncp1200. failure to do this will re-activate the dss in no-load conditions and standby power will be degraded. figure 1 offers a view of a typical bunch of pulses captured in standby at a 127 vdc input voltage. figure 1. a bunch of auxiliary pulses captured while the supply operates at no-load (vin = 127 vdc) 33 ms 200 m s 27 36 45 18 ncp1200 cvcc figure 2. the auxiliary is clamped to avoid exceeding the 16 v maximum rating rlimit laux caux 1n4148 15 v 32 1 as we previously stated, we want to deliver 70 w with a 16.5 v output level. the maximum rating for the ncp1200 states a level less than 16 v. as a result, the auxiliary vcc shall be less than 16v but also above vccon in any conditions to ensure full dss de-activation. a solution consists in artificially raising the ratio between the power winding and the auxiliary one to ensure adequate supply at no-load. we successfully tested a 0.9 ratio, where the auxiliary output gets clamped by a 15v zener diode in nominal operation. figure 2 shows the option. we measured a vcc of 11.5 v @ 230 vac and 12.2 v @ 90 vac. rlimit on figure 2 can easily be adjusted to move these values up or down, depending on the final winding ratios. care must be taken to avoid over-dissipation of the 15 v zener diode in nominal conditions. power supply, element-by-element design let's first detail the specs of our power supply: vin: 90265 vac vout: 16.8 v @ 4.2 a (pout = 70 w) short-circuit protection over-voltage protection efficiency > 80% pin = 70 / 0.8 = 87.5 the below sequence details step-by-step the calculation procedure for every component of the power supply. dc high-voltage rail from these above numbers, we can deduce the level of the high-voltage rail, neglecting the dual vf drop: v hv max 265 2 374 vdc v hv min 90 2 127 vdc figure 3. a typical ripple voltage over the bulk capacitor vripple vinpeak v hv avg 10 ms bulk capacitor figure 3 portrays the typical waveform captured across a bulk capacitor delivering power to a given charge. to simplify the calculation, we will neglect the char ging period and thus consider a total discharge time equal to 1/(2 ? fline). from the design characteristics, we can evaluate the equivalent current (iload) drawn by the charge at the lowest input line condition. let's us adopt a 40% ripple level, or a 50 v drop from the corresponding vin peak . to evaluate the equivalent load current (which discharges cbulk between
and8076/d http://onsemi.com 3 the peaks), we divide the input power by the average rectified voltage: iload pin vrect avg pout vpeak vripple 2
(1) 860 ma dc @ 90 vac input voltage thanks to figure 3 information, we can evaluate the capacitor value which allows the drop from vpeak down to vavg - (vripple/2) to stay within our 50 v target, dv ? c = i load ? dt: cbulk pout 2 fline vripple vpeak vripple 2
(2) 171 f or 180 f for a normalized value (fline = 50 hz worse case). diode bridge selection to select the right rectifiers, it is necessary to know the rms current flowing through its internal diodes. prior to reach this final result, we need to evaluate the diode conduction time. from figure 4, we can see that the diode starts to conduct when v ac in reaches vmin and stops when reaching vin peak : figure 4. when v ac in reaches vpeak, the diode stops conducting tc v min v inpeak vbulk 300 ma idiode x-2 ms/div v ac in from a mathematical point of view, we can calculate the time v ac in takes to reach vmin, with vmin = vpeak - vripple: v ac in sin( t) vmin since vpeak is reached at the input sinusoid top (or one fourth of the input period), then the diode conducting time tc is simply: tc 1 4 fline sin -1 vmin v ac in 2
360 fline (3) 3ms@vin 90 vac during these 3 ms, vbulk is the seat of a rising voltage equal to vripple or 50 vpp. this corresponds to a brought charge q of: qbulk vripple cbulk 9mc (4) from figure 4, we can calculate the amount of charge q drawn from the input by integrating the input current over the diode conduction time: qin tc 0 i diode (t).dt (5) the expression of i diode (t) is: ipeak tc t tc (6) after proper integration, it comes: qin 1 2 ipeak tc if we now equate qbulk and qin and solve for ipeak, it comes: ipeak qbulk 2 tc (7) or 6 a peak. we can now evaluate the rms current flowing through the diodes: irms fline tc 0 ( i diode (t) ) 2 dt (8) ipeak tc 3 2 fline 1.9a@vac 90 we selected a kbu4j diode bridge (600 v/4 a) for the rectifying function. a small resistor, or best an ntc, can however be put in series to limit the surge current (when you plug the smps in the ac outlet) to less than the diode maximum peak current (ifsm) or what the standard imposes you. thanks to these numbers, we compute the apparent power at low line: 1.9 a 90 v = 170 va which compared to our 87.5 watts of active power (neglecting the input diode bridge and cbulk losses) gives a power factor of: pf w v.a 0.51 (9) conform to what we could expect from this kind of offline power supply.
and8076/d http://onsemi.com 4 transformer calculation transformer calculation can be done in several manners: a) you evaluate all the transformer parameters, electrical but also physical ones, including wire type, bobbin stack-up etc. b) you only evaluate the electrical data and leave the rest of the process to a transformer manufacturer. we will adhere to the latest option by providing you with a list of potential transformer manufacturers you can use for prototyping and manufacturing. however, as you will discover, designing a transformer for smps is an iterative process: once you freeze some numbers, it is likely that they finally appear either over or under estimated. as a result, you re-start with new values and see if they finally fit your needs. to help you speed-up the transformer design, a design-aid spreadsheet is available from the on semiconductor web site, www.onsemi.com/pub/ncp1200. let's start the process with the turn ratio calculation. turn ratio and output diode selection the primary/secondary turn ratio affects several parameters: ? the drain plateau voltage during the off time: the lowest plateau gives room for the leakage inductance spike before reaching the mosfet's bvdss: vplateau np ns (vout vf) vindc max (10) ? the secondary peak inverse voltage (piv) is linked to the turn ratio and the regulated output voltage by: piv ns np vindc max vout (11) if you lower the plateau voltage, you will increase the reverse voltage the secondary diode must sustain. with these numbers in mind, you can tweak the turn ratio according to the mosfet bvdss and the diode maximum reverse voltage. a schottky diode represents a good choice, especially with a power supply that can possibly enter continuous conduction mode (ccm). the lack of reverse recovery loss and a low forward drop play in favor of this component. however, because of the metal-silicon junction, moderate breakdown voltages are available for a moderate cost. the mbr20100 represents an interesting choice since it welcomes two 100 v schottky in a to-220 package. being in thermal contact, a parallel wiring is possible. the 100 v v rrm lets us calculate the minimum turn ratio we can go down to, keeping an acceptable safety margin: n piv vout vindc max (12) np:ns 1:0.221. a final ratio of 1:0.166 offers an adequate safety margin (vreverse = 80 v max). the diode's conduction power is evaluating using the following formula: pdiode avg vf id avg rd id rms 2 (13) rather than manually calculating these numbers, we will see later on how a spice simulator can do the job for us. primary inductance and peak current for ac/dc adapters delivering this amount of power in a small place, it is of common practice to make the power supply enter ccm in the middle of the total ac range (around 180 vac in our case). when the input ac voltage diminishes, the on-time increases and the primary / secondary rms current go up. this implies a greater heatsink for the mosfet but also larger aluminum cans for the secondary filters. for this reason, a transition from discontinuous conduction mode (dcm) to ccm will be envisaged here. figure 5 depicts these different modes. different methods exist to find the point transition takes place (also called the critical or borderline point). the idea consists in finding the critical inductance lc that will make the supply enter ccm at 180 vac. from figure 5, we can write: ton lp ip vindc (14) toff lp ip n (vout vf) (15) figure 5. depending on the primary current at turn- on, the supply crosses various operating modes ccm l > lc 0 0 l > lc l = lc i l i l(avg) i p not 0 at turn on on off bcm dcm 0 before turn on d/fs dead-time time
and8076/d http://onsemi.com 5 500m 1.50 2.50 3.50 4.50 10.0u 30.0u 50.0u 70.0u 90.0u 2.00 6.00 10.0 14.0 v ramp -2.00 d c r drv cs radd2 radd1 r sense 2 1 150 3 figure 6. a very simple way to generate a ramp from a square wave signal figure 7. simulations show a capacitor voltage ramping up from a few hundred of mv up to nearly 5 v from the flyback formula, we obtain: ip 2 pout lp f sw (16) ip = primary peak current n = np / ns = 1/0.166 = 6 pout = output power h = efficiency lp = primary inductance fsw = switching frequency vf = secondary diode forward drop vindc vac ? 2 (neglecting ripple) combining equations 14, 15 and 16 we obtain an lp value to be in bcm at 180 vac input voltage: lp ( vout 2 2 vout vf vf 2 ) ( eff n 2 vin 2 ) [ pout [ ( n vout n vf vin ) 2 f sw ]] 2 (17) the numerical application gives a 484 m h inductance with a peak current of 2.36 a. the ncp1200 incorporates a skip-cycle feature that forces the controller to slice the switching pattern when the power supply drives light loads. depending on the system time constants, the recurrence of the burst can enter the audible frequency range. since the default skip-cycle takes place at one third of maximum peak current, it is better to avoid working at high peak current in normal operation. should noise still appear in skip mode, pin1 lets you select a different lower skip level (unfortunately to the detriment of the standby power) generating less mechanical noise. as a result, we slightly increased the primary inductance to 700 m h to further limit the noise in standby operation. mosfet selection the mosfet drain voltage sees, in normal operation, a maximum voltage of: vindc max (vout vf) n ip lleak clump (18) the first term represents the maximum rectified dc voltage and goes up to 375 v. the reflected voltage pushes further up by 101 v. summing up these levels gives a total steady-state drain voltage of 476 v. the last term in equation 18 depicts the leakage inductance action which further stresses the mosfet at the opening. if we select a 600 v device, it leaves more than 100 v for this leakage action. a clamping network will stop its rise anyway. a 2sk2843 from t oshiba can be a good choice. this is a t o-220 600 v 10 a component which features a 1.2 w rds (on) @ tj = 100 c. ramp compensation with a supply entering ccm together with a duty-cycle greater than 50%, we need to inject ramp compensation into the controller to prevent subharmonic oscillations. an easy way to generate a ramp, is to take the driving signal available from pin5 and integrate it through a rc network. figure 6 shows how to wire the components and figure 7 shows the signal obtain with a 18 k w / 1 nf rc time constant. to calculate the necessary amount of ramp m , several methods exist. we will stick to the standard one which consists in injecting between 50 and 75% of the off-time downslope. the calculation is as follow: primary off-slope: n (vout vf) lp 153 ma s (19) once reflected over rsense, it becomes: 50.5 mv / m s ( s' ) duty-cycle in ccm: d vout n vin vout 45% @ vin 120 vdc (20) from figure 6 network, the maximum voltage is given by r and radd1 + radd2. with a 11 v driving voltage delivered by the ncp1200, we recommend a 18 k w for r and 1 nf for c. these values offer an acceptable tradeoff in terms of power consumption but also in terms of noise immunity. the
and8076/d http://onsemi.com 6 corresponding time constant of 18 m s gives a ramp maximum peak voltage of: vcc vdrv 1 e 1
5v (21) with t = 0.45 1/61 k. this provides an available ramp level of 677 mv/ m s ( s ). by setting radd2 to 1 k w , radd1 can be computed using the following formula: radd1 1k s s m 22.5 k for m = 60%. final tweak gives an 18k w resistor for radd1. component constraints in this section, we will see how spice can help us to precisely determine all the component constraints and thus calculate the necessary amount of heatsink they need. the simulation schematic we adopted is given on figure 8 and shows the ncp1200 wired as recommended in the data sheet. please note that the simulation fixture has been simplified to allow faster simulation time. for instance, the tl431 and its network usually hamper the simulation time to find out the right operating point. a zener diode and a resistor help finding it in a much quicker way. 27 36 45 18 ncp1200 vinput 120 + 21 hv ncp1200 fs = 65 k r8 1.0 k r9 18 k r5 100 m cvcc 47 m f ic = 14 + 12 vcc drv c6 1.0 nf r10 18 k d1 1n4148 vsense rsense 0.33 5 drv rg 10 23 16 18 20 istartup 10 + vdrain idrain iclp d4 mur160 r2 4.7 k c3 100 nf vclamp vadj lleak 12 m h lp 700 m h 24 iprim d r3 200 m 7 + 4 x1 xfmr ratio = -0.166 isec 15 x6 mbr20100 resr1 11 m iripple1 1 9 c1 3.3 mf ic = 16.5 vfb d3 1n963 x5 sfh610a 14 19 r15 1.0 k vsec l1 100 m h 31 r10 10 m 17 + iout resr2 300 m iripple2 32 c2 220 m f ic = 16.5 rload 3.7 vout vout 8 figure 8. the simplified simulation schematic helps to determine all the component key parameters d
and8076/d http://onsemi.com 7 figure 9. complete simulation results of the 70 w converter operated at 120 vdc input voltage 2.01 m 2.03 m 2.05 m 2.07 m 2.09 m 3.00 2.00 1.00 0 -1.00 2.40 2.00 1.60 1.20 800 m 10.00 6.00 2.00 -2.00 -6.00 156 154 152 150 148 123 4 1 2 3 4 idrain iprim iripple1 vclamp rms = 1.10 amps between 2.05 m and 2.06 m secs rms = 1.53 amps between 2.05 m and 2.06 m secs rms = 4.65 amps between 2.04 m and 2.05 m secs y (mean) = 152 volts x (first) = 2.00 m secs important results appear in figure 9. please note that the maximum rms current occur at the lowest line where the duty-cycle is pushed to the limit. as you can see, the ramp compensation works fine and no subharmonic oscillations can be noted. once everything is extracted, below are summarized the most important design constraints: mosfet rdson @ 100 c = 1.2 ohms rthetajc = 2.8 c/w pcond = 1.2 * 1.1 2 = 1.5 w the conduction losses are the strongest at low line. the total simulated losses, including switching events are evaluated to be around 2.6 w. further breadboard measurements confirmed this number. if we want to keep the junction temperature around 100 c at an ambient of 50 c, then we shall add a proper heatsink according to the following calculation: 15 c w r heatsink- air (tj max tamb max ) p r junction- case r case- heatsink lower r q heatsink- air resistances can of course be selected to run the device cooler. diode the mbr20100 welcomes two diodes that share nearly equal current thanks to their equal forward drops. the total forward drop dissipation will remain the same but the rms losses sensitive to the dynamic resistance will divide by two: i rms total = 6.8 a i av g total = iout = 4.2 a rd @ 3.4 a rms = 27 m w vf @ 2.2 a avg = 0.7 v pcond for one diode = 3.4 2 0.027 + 2.2 0.7 = 1.85 w or 3.7 w for the whole t o-220 package. simulations gives a bit less to 3.4 w. heat calculations (tj < 100 c and 50 c ambient) recommend a heatsink of 8 c/w for the mbr20100. as stated before, lower r q heatsink- air resistances can of course be selected to run the device cooler. capacitors icapacitor rms = 5 a the paralleling of capacitors will help achieve the right ripple current shared between all the devices. we selected three 2.2 mf capacitors capable of handling 1.7 arms each.
and8076/d http://onsemi.com 8 transformer below are the key parameters you will pass to your transformer manufacturer to help him select the right winding size and tailor the internal gap: maximum peak primary current, including 160 ns propagation delay: 1 / 0.33 + 374 160 n / 700 m = 3.2 a maximum primary rms current at low line: 1.6 a maximum secondary rms current: 6.9 a primary inductance: 700 m h turn-ratio, power section: np:ns = 1:0.166 turn-ratio, auxiliary section: np:naux = 1:0.15 clamping network the clamping network can be calculated using the following formulae: rclamp (22) cclamp vclamp vripple f sw rclamp (23) 2 vclamp (vclamp (vout vf sec) n) lleak ip 2 f sw the power dissipated by rclamp can also be expressed by: p rclamp 1 2 lleak ip 2 f sw vclamp (vout vf sec) n vclamp (vout vf sec) n 1 (24) with: vclamp: the desired clamping level; ip: the maximum peak current (e.g. during overload); vout + vf: the regulated output voltage level + the secondary diode voltage drop; lleak: the primary leakage inductance; n: the ns:np conversion ratio; fsw: the switching frequency; vripple: the clamping ripple, could be around 20 v. with a measured leakage inductance of 12 m h and a final clamping level of 150 v, rclamp is found to be 4.7 k w /6 w and cclamp 100 nf. the rms current flowing through cclamp is 220 ma. rc networks are economical clamping devices and care must be taken to not exceed the mosfet bvdss in the most stringent conditions, e.g. a cold startup sequence at high line. worse case arises when ip is maximum and vout reaches the target. stability analysis the stability analysis can be investigated using different approaches. spice has proven to be rather accurate for feedback loop analysis with smps. we will use the ncp1200 average model which is available to download from our web site (www .onsemi.com/pub/ncp1200). figure 10 shows the simulation template where the feedback network on the tl431 has been simplified to a simple 100nf capacitor. thanks to average modeling, the simulation time is kept short and results are delivered in a snap-shot, as testified by figure 11. figure 12 unveils the results obtained using a network analyzer and confirms the validity of our approach (vin = 240 vac). stability has been checked at various line/loads combinations and gave good results. final transient step did not reveal any overshoot or unwanted oscillations. the adapter schematic the final schematic implements a current-mode flyback architecture, driving a 600 v mosfet. the 2sk2545 features a 10 a capability but a 6.0 a/600 v can also be mounted, such as the fqp6n60 from fairchild but to the expense of increased conduction losses. figure 13 offers a complete view of the electrical sketch. the board can actually be used with either auxiliary or without auxiliary winding. by removing the resistance r4, you reactivate the dss on a ncp120x controller featuring this ability. the board can therefore accept the following controllers: ncp1200, featuring dss. ncp1200a, featuring dss. ncp1203, auxiliary winding only. ncp1216, featuring dss and internal ramp compensation. improved emi jittering with dss. ncp1217, auxiliary winding only, internal ramp compensation. on ncp1216 and 1217, the internal ramp compensation avoids using the external circuitry made of r1-r7-d4 and c10. if one of these two parts are plugged in the demoboard, you must disable this network by simply disconnecting r1 and growing r6 up to 2.7 k w (for a 65 khz operation). the ncp120x takes place with two other bipolars that implement a discrete scr, activated in presence of an ovp, e.g. an optocoupler failure. d5 senses the overvoltage condition and can easily be adjusted to fit any other levels. thanks to r10, the ovp permanently latches-off the supply and the user shall cycle v cc off and on again to restart the supply. shutdown is obtained by pulling the feedback pin down thr ough d6. the clamp resistor is split in two dif ferent components to avoid an excessive heat burden on one single device. both main mosfet and secondary diode are mounted on an adequate heatsink to evacuate the heat. to ease the designer task, or simply help evaluating the board performance faster, we have experimented different transformers, available through appendix b manufacturers. please note that some include the auxiliary winding for dss deactivation whereas other only offer a dual winding arrangement where the dss no longer activates and offers the best standby power. all details are given in appendix b. the final demoboard will not accommodate with all these transformers simply because multiple footprints was not possible. they however have all been tested okay. measurements were taken with the coilcraft transformer. as a final note, the actual demoboard delivers 19 vdc/70 w versus the original design-based 16.5 v. as a result, figure 1b circuit has been replaced by l3-r13 and c12 to improve the short-circuit protection when using an auxiliary winding. output voltage can be adjusted by changing the feedback network made of r12/r20/r21.
and8076/d http://onsemi.com 9 x5 tl431 15 c1 100 nf vout r5 4.7 k r15 1.0 k rlow 6.8 k rupp 39 k out2 out1 5 10 13 c5 1.0 nf x3 sfh610a 2.93 16.1 15.4 2.50 lol 1.0 kh vin vin 350 + col 1.0 kf + vstim ac = 1 14 0 340 1 ctrl fb gnd in 2.93 out ncp1200 averaged 11 12 x1 ncp1200_av fs = 61 k l = 700 m mc = 39605 ri = 0.33 x1x xfmr ratio = 0.166 105 4 2 17.5 d1 mbr20100ct 16.9 out1 resr1 30 m 16.9 7 c1 5.8 mf l1 10 m h 16.9 rs 10 m 16.8 out2 r17 300 m 16.8 9 c2 100 m f rload 4.2 16.8 + iout figure 10. the simulation schematic for our 70 w current-mode power supply gain figure 11. simulated bode plot of the current mode flyback 48.0 24.0 0 -24.0 -48.0 0 10 1 k 10 k 100 k 160 80.0 0 -80.0 -160 phase mag (db) 48.0 36.0 24.0 12.0 0 -12.0 -24.0 -36.0 -48.0 160.0 120.0 80.0 40.0 0 -40.0 -80.0 -120.0 -160.0 phase (deg) 10 100 1 k 10 k 100 k figure 12. measured open-loop gain with a network analyzer mag phase
and8076/d http://onsemi.com 10 figure 13. the simulation schematic for our 70 w current-mode power supply c7 27 36 45 18 adj fb cs gnd hv vcc drv c23 1.0 nf* d6 bat54 d5 27 v c11 10 nf r8 10 k 2n2222 q2 r5 10 k 2n2907 q1 ovp (optional) + c3 220 m f r3 1 m c2 x2 470 nf r6 1.0 k 2.2 r2 5 w, fuse type b1 2kbp08m 2 27 mh l2 * ic3 r10 12 k r1 18 k ramp comp if needed + r7 18 k d9 15 v d4 1n4148 c24 47 m f c10 1.0 nf r4 220 c1 100 nf r1a 39 k r1b 39 k d8 mur160 + l3 47 m h r9 47 19 v @ 3.6 a gnd d1 mbr20100 + + + 2200 m f c5 c6 l1 10 m h lp = 700 m h t1 1:0.15 for np:ns_aux 1:0.166 for np:ns_power + r7a, b, c 0.33, total 1 w ic1 sfh6156-2 3 1 smd // c25 2.2 nf y1 type r21 5.6 k r11 1.0 k c9 100 nf c8 open r19 open m1 fqp6n60 2 39 k 3 w in // c220 220 m f r18 1.0 k r12 27 k ic2 tl431 universal input d3 1n4148 r13 1.5 k c12, 10 nf d2 r20 10 k * = close to the ic c4 100 m f
and8076/d http://onsemi.com 11 figure 14. line regulation is excellent thanks to current mode and a good open-loop dc gain figure 15. load regulation at two different input voltages 20 16.715 16.730 16.740 16.745 16.750 16.755 16.760 16.765 output voltage (v) 16.735 output power (w) 40 60 80 16.725 16.720 0 240 vac 110 vac 16.700 16.705 16.715 16.720 16.725 16.730 16.735 16.740 output voltage (vdc) 16.710 100 input voltage (vac) 120 140 160 180 200 220 240 board final results standby power measured on an infratek watt-meter operated in watt-hour accumulation mode for best accuracy (run length = 30 minutes). vin = 120 vac, vout = 16.76 v, iout = 0 pin = 78 mw vin = 240 vac, vout = 16.76 v, iout = 0 pin = 84 mw line regulation the array in figure 14 shows the performance when the input voltage is moving between both range ends. as one can see, current mode control with good open- loop gain ensures a d vout less than 1 mv for a 212 vdc input variation (-106 db dc audio susceptibility). load regulation by varying the load current between 11 w and 70 w, it is possible to plot the load regulation of the board as shown in figure 15. efficiency we have designed two boards, one using the auxiliary winding for best standby performance, and another one with the dynamic self-supply (dss) left normally working. because of the auxiliary winding, it has been necessary to further clamp the drain voltage in order to improve the primary overload detection. it is not necessary with the dss and therefore the rcd drain clamp network can be less aggressive, thus slightly improving the efficiency. board 2 also features a 6 a mosfet compared to a 3 a mosfet on board 1. board 1, aux. winding: vin = 110 vac, h = 79% vin = 240 vac, h = 83.5% board 2, dss: vin = 110 vac, h = 83.4% vin = 240 vac, h = 84.8%
and8076/d http://onsemi.com 12 appendix a, bill of material all resistors are 5% 1/4 w smd 1206 unless otherwise noted. all smd capacitors are 1206 smd 16 v types unless otherwise noted. all through-hole electrolytic capacitors are radial types unless otherwise noted. manufacturer references are given for specific components only. r1 18 k w - r2 2.2 w , 5.0 w fuse resistor or 3.15 a/250 v t fuse - r1a, b 39 k w , 3.0 w, pro3, thru holes - r3 1.0 m w (not wired on demo) - r4 220 w - r5 10 k w - r6 1.0 k w - r7 18 k w - r7a, b, c 1.0 w 1.0 w smd - r8 10 k w - r9 47 w , thru holes - r10 12 k w - r11 1.0 k w - r12 27 k w , thru holes - r13 1.5 k w - r18 1.0 k w , thru holes - r19 not wired, open for feedback options - r20 10 k w - r21 5.6 k w - c1 100 nf/400 v - c2 470 nf/x2 security device - c3 220 f/400 v snap-in philips 2222-157-46221 c4 100 f/35 v - c5 2200 f/25 v/radial philips 2222-136-50222 c6 2200 f/25 v/radial philips 2222-136-50222 c7 2200 f/25 v/radial philips 2222-136-50222 c8 not wired, open for feedback options - c9 100 nf - c10 1.0 nf - c11 10 nf - c12 10 nf - c22 470 f/35 v/radial - c23 1.0 nf - c24 47 f/25 v/radial - c25 2.2 nf-y1 security device - b1 600 v-4.0 a diode bridge kbu4j general semi d1 mbr20100 on semiconductor d2 1n4148 - d3 1n4148 - d4 1n4148 - d5 27 v/400 mw on semiconductor d6 bat54 - d8 mur160 on semiconductor d9 15 v/400 mw - ic1 sfh6156-2 infineon ic2 tl431 to-92 on semiconductor ic3 ncp1200p60 on semiconductor q1 2n2907 on semiconductor q2 2n2222 on semiconductor l1 pcv-2-103-05 coilcraft l2 b82724-a2142-n1 epcos l3 47 h 47 h m1 2sk2543 (toshiba) or fqp6n60 (fairchild) - t1 z9260-a or z9007-b coilcraft heatsink 1 kl194/38,1 sw (diode) seifert heatsink 2 kl195/38,1 sw (mosfet) seifert
and8076/d http://onsemi.com 13 appendix b, transformer manufacturers eldor corporation headquarter via plinio 10, 22030 orsenigo (como) italia tel. : +39-031-636 111 fax : +39-031 636 280 eldor@eldor.it www.eldor.it ref. : 2074.5059a, no aux. winding, p = 70 w pulse engineering site d'orgelet zone industrielle 39270 - orgelet tel. : 33 (0)3 84 35 04 04 fax: 33 (0)3 84 25 46 41 http://www.pulseeng.com/ email: vpelletier@pulseeng.com ref. : pf0082, with auxiliary winding, p = 50 w ref. : pf0091, without auxiliary winding, p = 50 w coilcraft 1102 silver lake road cary, illinois 60013 usa tel: (847) 6396400 fax: (847) 6391469 email: info@coilcraft.com http://www.coilcraft.com ref. : z9260-a, with auxiliary winding, p = 70 w ref. : z9007-b, without auxiliary winding, p = 70 w thomson multimedia - orega route de noiron b.p. 24 70101 gray cedex - france tel : 33 (0)3 84 64 54 26 fax: 33 (0)3 84 65 18 45 www.thomsonmultimedia.com email: bouillotj@thmulti.com ref. : g7086-01, no aux. winding, p = 70 w for lower volumes: atelier special de bobinage 125 cours jean jaurs 38130 echirolles - france tel. : 33 (0)4 76 23 02 24 fax: 33 (0)4 76 22 64 89 email: asb@wanadoo.fr ref. : ncp120035 wum, no aux. winding, rm10 p = 35 w
and8076/d http://onsemi.com 14 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. typicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including typicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2-9-1 kamimeguro, meguro-ku, tokyo, japan 153-0051 phone : 81-3-5773-3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. and8076/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 800-282-9855 toll free usa/canada

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